Exploration of hardware topologies based on functions, variability and timing

abstract

This paper gives an overview over a dissertation project in the area of design space exploration for distributed, embedded systems. As the engineering of distributed embedded systems is getting more and more complex due to increasingly sophisticated functionalities demanding more and more powerful hardware, automation is required in order cope with this rising complexity. Using a model based systems engineering approach enables design space exploration methods which provide such automations, given a formalization of the problem in order to be solvable e.g. by SMT solvers. In this thesis we want to provide an automated synthesis of hardware topologies (E/E architectures) based on the functions which are deployed onto this topology and constraints and optimization objectives which are derived from the requirements of the system. The synthesis shall consider variability aspects (possible variants) of the hardware elements. Additionally, timing aspects of the deployed shall be regarded such that the solution of the synthesis is a hardware topology, a deployment of functions onto this topology and a schedule of these functions. The thesis shall be evaluated by using an automotive industrial use case of realistic size.